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1/19 october 2004 VND920-E double channel high side solid state relay rev. 1 table 1. general features (*) per channel with all the output pins connected to the pcb. cmos compatible input proportional load current sense shorted load protection undervoltage and overvoltage shutdown overvoltage clamp thermal shutdown current limitation protection against loss of ground and loss of v cc very low stand-by power dissipation reverse battery protection (**) in compliance with the 2002/95/ec european directive description the VND920-E is a double chip device made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. built-in analog current sense output delivers a current proportional to the load current. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (**) see application schematic at page 9. type r ds(on) i out v cc VND920-E 16m ? 35 a (*) 36 v so-28 (double island) package tube tape and reel powerso-10 ? VND920-E vnd920 tr-e
VND920-E 2/19 figure 2. block diagram undervoltage overtemperature v cc 1 gnd 1 input 1 output 1 overvoltage current limiter logic driver power clamp v cc clamp v ds limiter detection detection detection k i out current sense 1 undervoltage overtemperature v cc 2 gnd 2 input 2 output 2 overvoltage current limiter logic driver power clamp v cc clamp v ds limiter detection detection detection k i out current sense 2
3/19 VND920-E table 3. absolute maximum ratings (per each channel) note: 1. per island table 4. configuration diagram (top view) & suggested connections for unused and n.c. pins symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 21 a i in dc input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v v esd electrostatic discharge (human body model: r=1.5k ?; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v e max maximum switching energy (l=0.25mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i l =45a) 355 mj p tot power dissipation t l 25c 6.25 (see note 1) w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c connection / pin current sense n.c. output input floating x x x to ground through 1k ? resistor x through 10k ? resistor v cc 1 gnd 1 input 1 current sense 1 nc v cc 1 v cc 2 gnd 2 input 2 current sense 2 v cc 2 v cc 2 output 2 output 2 output 2 output 2 output 1 output 1 output 1 output 1 v cc 1 output 2 output 2 output 1 output 1 nc nc nc 1 14 15 28
VND920-E 4/19 figure 3. current and voltage conventions table 5. thermal data note: (1) when mounted on a standard single-sided fr-4 board with 1cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. note: (2) when mounted on a standard single-sided fr-4 board with 6cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. electrical characteristics (8v 5/19 VND920-E electrical characteristics (continued) table 7. switching (v cc =13v) table 8. logic input table 9. v cc - output diode table 10. protections (see note 3) note: 3. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min typ max unit t d(on) turn-on delay time r l =1.3 ? (see figure 2) 50 s t d(off) turn-off delay time r l =1.3 ? (see figure 2) 50 s dv out / dt (on) turn-on voltage slope r l =1.3 ? (see figure 2) see relative diagram v/ s dv out / dt (off) turn-off voltage slope r l =1.3 ? (see figure 2) see relative diagram v/ s symbol parameter test conditions min typ max unit symbol parameter test conditions min typ max unit v il input low level 1.25 v i il low level input current v in =1.25v 1 a v ih input high level 3.25 v i ih high level input current v in =3.25v 10 a v i(hyst) input hysteresis voltage 0.5 v symbol parameter test conditions min. typ. max. unit v f forward on voltage -i out =5a; t j =150c 0.6 v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c i lim dc short circuit current v cc =13v 5v VND920-E 6/19 electrical characteristics (continued) table 11. current sense (9v v cc 16v) (see fig. 4) note: 4. current sense signal delay after positive input slope symbol parameter test conditions min typ max unit k 1 i out /i sense i out =1a; v sense =0.5v; t j = -40c...150c 3300 4400 6000 dk 1 /k 1 current sense ratio drift i out =1a; v sense =0.5v; t j = -40c...+150c -10 +10 % k 2 i out /i sense i out =10a; v sense =4v; t j =-40c t j =25c...150c 4200 4400 4900 4900 6000 5750 dk 2 /k 2 current sense ratio drift i out =10a; v sense =4v; t j =-40c...+150c -8 +8 % k 3 i out /i sense i out =30a; v sense =4v; t j =-40c t j =25c...150c 4200 4400 4900 4900 5500 5250 dk 3 /k 3 current sense ratio drift i out =30a; v sense =4v; t j =-40c...+150c -6 +6 % i senseo analog sense leakage current v cc =6...16v; i out =0a;v sense =0v; t j =-40c...+150c 010 a v sense max analog sense output voltage v cc =5.5v; i out =5a; r sense =10k ? v cc >8v; i out =10a; r sense =10k ? 2 4 v v v senseh sense voltage in overtemperature conditions v cc =13v; r sense =3.9k ? 5.5 v r vsenseh analog sense output impedance in overtemperature condition v cc =13v; t j >t tsd ; all channels open 400 ? t dsense current sense delay response to 90% i sense (see note 4) 500 s
7/19 VND920-E figure 4. i out /i sense vs. i out figure 5. switching characteristics (resistive load r l =1.3 ? ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3000 3500 4000 4500 5000 5500 6000 6500 min.tj=-40c max.tj=-40c min.tj=25...150c max.tj=25...150c typical value i out (a) i out /i sense v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
VND920-E 8/19 table 12. truth table (per each channel) table 13. electrical transient requirements on v cc pin conditions input output current sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp l l 0 iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5ceee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
9/19 VND920-E figure 6. waveforms sensen inputn normal operation undervoltage v ccn v usd v usdhyst inputn overvoltage v ccn sensen inputn sensen load currentn load currentn load currentn overtemperature inputn sensen t tsd t r t j load currentn v ov v ovhyst v cc > v usd short to ground inputn load currentn sensen load voltagen inputn load voltagen sensen load currentn VND920-E 10/19 figure 7. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc1 output2 c. sense 1 d ld +5v r prot output1 r sense1,2 input1 c. sense 2 input2 c r prot r prot r prot d gnd r gnd v gnd gnd1 gnd2 v cc2
11/19 VND920-E figure 8. off state output current figure 9. high level input current figure 10. input clamp voltage figure 11. on state resistance vs t case figure 12. on state resistance vs v cc figure 13. input high level -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 1 2 3 4 5 6 7 8 9 il(off1) (ua) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) iout=10a vcc=8v; 36v 5 10152025303540 vcc (v) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) tc= - 40oc tc= 25oc tc= 150oc -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v)
VND920-E 12/19 figure 14. input low level figure 15. turn-on voltage slope figure 16. overvoltage shutdown figure 17. input hysteresis voltage figure 18. turn-off voltage slope figure 19. i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 250 300 350 400 450 500 550 600 650 700 dvout/dt(on) (v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 50 100 150 200 250 300 350 400 450 500 550 dvout/dt(off) (v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 10 20 30 40 50 60 70 80 90 100 ilim (a) vcc=13v
13/19 VND920-E figure 20. maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 ? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
VND920-E 14/19 so-28 double island thermal data figure 21. double island pc board table 14. thermal calculation according to the pcb heatsink area r tha = thermal resistance junction to ambient with one chip on r thb = thermal resistance junction to ambient with both chips on and p dchip1 =p dchip2 r thc = mutual thermal resistance figure 22. r thj-amb vs. pcb copper area in open box free air condition chip 1 chip 2 t jchip1 t jchip2 note on off r tha x p dchip1 + t amb r thc x p dchip1 + t amb off on r thc x p dchip2 + t amb r tha x p dchip2 + t amb on on r thb x (p dchip1 + p dchip2 ) + t amb r thb x (p dchip1 + p dchip2 ) + t amb p dchip1 =p dchip2 on on (r tha x p dchip1 ) + r thc x p dchip2 + t amb (r tha x p dchip2 ) + r thc x p dchip1 + t amb p dchip1 p dchip2 layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m, copper areas: 0.5cm 2 , 3cm 2 , 6cm 2 ). 10 20 30 40 50 60 70 01234567 pcb cu heatsink area (cm ^2)/island rt hj_am b (c/w) r tha r thb r thc
15/19 VND920-E figure 23. so-28 thermal impedance junction ambient single pulse figure 24. thermal fitting model of a two channels hsd in so-28 pulse calculation formula table 15. thermal parameter one channel on two channels on on same chip 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time(s) zth(c/w) one channel on tw o channels on 6 cm ^2/is land 3 cm ^2/is land 0,5 cm ^2/is land t_amb pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r2 c1 c2 r1 tj_1 tj_2 area/island (cm 2 )0.56 r1= (c/w) 0.02 r2= (c/w) 0.1 r3= (c/w) 2.2 r4= (c/w) 11 r5= (c/w) 15 r6= (c/w) 30 13 c1= (w.s/c) 0.0015 c2= (w.s/c) 7.00e-03 c3= (w.s/c) 1.50e-02 c4= (w.s/c) 0.2 c5= (w.s/c) 1.5 c6= (w.s/c) 5 8 z th r th z thtp 1 ? () + ? = where t p t ? =
VND920-E 16/19 package mechanical table 16. so-28 mechanical data figure 25. so-28 package dimensions symbol millimeters min typ max a 2.65 a1 0.10 0.30 b 0.35 0.49 b1 0.23 0.32 c0.50 c1 45 (typ.) d 17.7 18.1 e 10.00 10.65 e1.27 e3 16.51 f 7.40 7.60 l 0.40 1.27 s8 (max.)
17/19 VND920-E figure 26. so-28 tube shipment (no suffix) figure 27. tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 28 bulk q.ty 700 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 a c b base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions
VND920-E 18/19 revision history date revision description of changes oct. 2004 1 - first issue.
19/19 VND920-E information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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